The disclosure generally relates to a timing analysis approach of an integrated circuit and, more particularly, to a timing analysis approach capable of simplifying the analysis process while increasing the accuracy of the analysis.
Many semiconductor manufacturers or software developers create a standard cell library for widely-used circuit elements and provide characteristics for those standard cells. Accordingly, when adopting those standard cells, the circuit designer is enabled to accurately estimate the electrical characteristics of the circuit elements and the timings of the signals processed by the circuit elements, so that a desirable integrated circuit can thus be designed.
As is well known in related art, at least some circuit blocks in the analog circuit or mixed signal circuit are specially designed by the circuit designer rather than being realized with the standard cells. Therefore, when the circuit designer wants to analyze the signal timings of the analog circuit or mixed signal circuit, it is required to conduct simulation analysis for the entire circuit by inputting clock signals of different patterns into the circuit in order to figure out the killer pattern that affects the signal timings. However, the traditional timing analysis approaches are complicated and time-consuming. Furthermore, once the simulation is performed based on a pattern other than the correct killer pattern, it may be unable to locate some timing errors of the integrated circuit, thereby causing malfunction to the integrated circuit.